This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2000-111039, filed Apr. 12, 2000, the entire contents of which are incorporated herein by reference.
The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a MIS (Metal Insulator Semiconductor) FET (Field Effect Transistor) including a power MOS (Metal Oxide Semiconductor) FET, which is required to have a high breakdown voltage.
In recent years, market forces have demanded that power MOSFETs used in invertors for electrical vehicles (EV) and the like be more compact, less energy-consuming, and less expensive.
In the field of MOSFETs subjected to such requirements, a MOSFET having a structure shown in FIG. 3 is known as one which can solve the problem of trade-off between the breakdown voltage and the ON-resistance of the device. This device includes an n-drain layer 101, which has p-embedded epitaxial layers 102 arrayed in multi stages. With this arrangement, the n-drain layer 101 decreases its resistance. Further, the n-drain layer 101 and the p-layers 102 are completely depleted by expansion of depletion layers from pn junctions between the p-layers 102 and the n-layer 101, in a reverse bias state (RESURF (REduced SURface Field) principle.
Other than this structure, similar structures have been proposed, such as one having diffusion layers called p-pillar/n-stripe formed in an n-drain layer. These structures are constituted on the basis of the following definition.
[Structure Definition 1]
The following formula (1) is satisfied.
Vxcex93(V)dV≅nixe2x80x83xe2x80x83(1) 
where v is the volume of a drain layer, xcex93 (v) is the activated impurity concentration in the drain layer, ni is the activated impurity concentration in intrinsic semiconductor Si (ni≈1011 cmxe2x88x923), and xe2x80x9c≅nixe2x80x9d corresponds to the activated impurity concentration in the I layer of a PIN diode (xe2x80x9c≅nixe2x80x9d≈1011 to 1015 cmxe2x88x923)
And the following formula (2) is also satisfied.
E(BVDSS) less than Ecrit for ∀Vxe2x80x83xe2x80x83(2) 
This is alterable to the following formulas (3) and (4).
∫{right arrow over (r)}P({right arrow over (r)})d{right arrow over (r)} less than Qcritxe2x80x83xe2x80x83(3) 
∫{right arrow over (r)}N({right arrow over (r)})d{right arrow over (r)} less than Q critxe2x80x83xe2x80x83(4) 
where {right arrow over (r)} is the directional vector of the drain layer in a microscopic-aspect, P({right arrow over (r)}) is the activated p-type impurity concentration in the drain layer, N({right arrow over (r)}) is the activated n-type impurity concentration in the drain layer, Ecrit=2xc3x97105 [v/cm], Qcrit=1.5xc3x971012 [/cm2], and BVDSS is the maximum electric field intensity at a junction when a breakdown voltage is applied to a device.
However, MOSFETs having the structure described above entail a problem involving a difficulty in controlling the impurity profile in the n-drain layer. More specifically, in order to realize the RESURF principal, it is necessary to satisfy the following conditions. First, the activated impurity concentration in the n-drain layer, which comes from an offset between a p-type impurity and an n-type impurity, needs to be close to the activated impurity concentration in the I (intrinsic) layer of a PIN diode. In the Structure Definition 1, the activated impurity concentration in the I layer is denoted by xe2x80x9c≅nixe2x80x9d. Furthermore, in a reverse bias state, all the regions in the n-drain layer are completely depleted and the electric field intensity E satisfies E less than Ecrit in all the regions. Note that Ecrit mentioned above and also shown in the Structure Definition 1 denotes an electric field intensity at which an avalanche starts in Si.
As described above, although an attempt has been made to provide a device with both of a high breakdown voltage and a low ON-resistance, the prior art entails a problem that there is a difficulty in controlling the impurity profile in the n-drain layer to realize the RESURF principal.
An object of the present invention is to provide a semiconductor device and a manufacturing method thereof, which can realize the RESURF principal without controlling the impurity profile in a semiconductor layer, and can easily obtain both of a high breakdown voltage and a low ON-resistance.
According to a first aspect of the present invention, there is provided a semiconductor device comprising:
a first semiconductor layer of a first conductivity type;
a second semiconductor layer of the first conductivity type having an impurity concentration lower than that of the first semiconductor layer, and disposed on the first semiconductor layer;
a third semiconductor layer of a second conductivity type, formed in a surface of the second semiconductor layer on a side reverse to the first semiconductor layer;
a fourth semiconductor layer of the first conductivity type formed in a surface of the third semiconductor layer;
a gate electrode facing, through a gate insulating film, a surface of the third semiconductor layer between the second and fourth semiconductor layers;
a first electrode electrically connected to the fourth semiconductor layer;
a second electrode electrically connected to the first semiconductor layer, such that the second semiconductor layer is sandwiched between the first and second electrodes; and
a plurality of hetero regions having a dielectric constant higher than that of the second semiconductor layer, and disposed in the second semiconductor layer between the first and second electrodes.
According to a second aspect of the present invention, there is provided a MISFET comprising:
a drain layer of a first conductivity type having first and second sides reverse to each other;
a base layer of a second conductivity type disposed on the drain layer on the first side;
a source layer of a first conductivity type disposed on the base layer;
a gate electrode facing, through a gate insulating film, a channel region, which is part of the base layer between the drain and source layers;
a source electrode electrically connected to the source layer;
a drain electrode electrically connected to the drain layer on the second side, such that the drain layer is sandwiched between the source and drain electrodes; and
a plurality of hetero regions having a dielectric constant higher than that of the drain layer, and disposed in the drain layer between the source and drain electrodes, the hetero regions being arranged to lower an electric field in the drain layer when a reverse bias is applied between the source and drain electrodes, thereby improving a breakdown voltage of the MISFET, as compared to a case where no hetero regions are formed.
According to a third aspect of the present invention, there is provided a method of manufacturing a semiconductor device according to the first aspect wherein the hetero regions comprise hollow portions formed in the second semiconductor layer, comprising:
a first step of forming a first epitaxial layer of the first conductivity type on the first semiconductor layer;
a second step of forming a plurality of trenches in a surface of the first epitaxial layer;
a third step of closing upper portions of the trenches by performing hydrogen annealing, thereby forming a plurality of hollow portions; and
a fourth step of forming a second epitaxial layer of the first conductivity type on the first epitaxial layer with the hollow portions formed therein.
By the semiconductor device and the manufacturing method thereof, according to the present invention, it is possible to control the average concentration of the second semiconductor layer or the drain layer to be xe2x80x9c≅nixe2x80x9d without controlling the impurity profile. Consequently, the electric field in the bulk of the second semiconductor layer or the drain layer is lowered to a level where it does not cause an avalanche in effect, when a reverse bias is applied.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.